Ethernet Schematic Design for Allwinner T113

In embedded industrial control and IoT applications, the Ethernet interface is a core module for achieving high-speed data communication. With its excellent industrial-grade performance and rich peripheral interfaces, the Allwinner T113 chip is frequently used in various network terminal designs. This article analyzes the key points of schematic design based on the practical application circuit of the T113 and the IP101GR PHY chip.

1、 Hardware Architecture Overview

This design adopts the RMII (Reduced Media Independent Interface) mode to connect the Allwinner T113 processor with the IP101GR PHY chip. Due to its low pin count and simple routing, the RMII interface has become the preferred solution for the T113 to implement 100M Ethernet. The system mainly consists of three parts: the PHY core control circuit, the clock configuration circuit, and the network transformer/RJ45 interface circuit.

2、 Key Circuit Design Analysis

2.1 IP101GR PHY Core Configuration

As shown in Figure 1, the operating mode of the IP101GR is configured through pull-up/pull-down resistors on the pins.

● Mode Selection: The circuit ensures the PHY operates in RMII mode by configuring the voltage levels of the COL/RMII and CRS pins.

● Reset and Enable: The RESET_N pin is connected to the T113's GPIO for software reset management of the system.

● Power and Filtering: The VCC-EPHY-3V3 power pin must be equipped with decoupling capacitors (such as 10uF and 100nF in parallel) to filter out high-frequency noise and ensure the stability of the PHY's internal analog circuits.

Figure 1 T113 connection to PHY chip

2.2 Clock Circuit Design

Ethernet communication has extremely high requirements for clock accuracy. In the schematic:

Clock Source Selection: The circuit adopts the "Default use SoC 25M CLKOUT" scheme, which directly uses the 25MHz clock signal output by the Allwinner T113 for the X1 pin of the PHY. This eliminates the need for an external crystal oscillator on the PHY side, effectively reducing costs and component footprint.

Routing Requirements: The design document specifically emphasizes that the clock signal line (such as EPHY-CLK-25M) should be as close to the chip pins as possible and treated with ground shielding to prevent data transmission errors caused by clock jitter.

2.3 Network Transformer and RJ45 Interface

● The network transformer (such as PM44-11BP) is mainly used for signal isolation and impedance matching, which is directly related to EMC performance.

● Differential Signal Processing: As shown in Figure 2, before the MDI differential pair signals of the PHY chip enter the network transformer, 51Ω matching resistors are connected in series, and ESD protection devices (ESD9B5VL-2/TR) are added to suppress electrostatic discharge.

● Center Tap Filtering: The center tap of the network transformer is grounded through a 100nF capacitor, which must meet high-voltage withstand ratings. Meanwhile, the shielding ground (PGND) of the RJ45 should be connected to the chassis ground (CHASSIS GND) via a high-voltage capacitor (1000pF/2KV) to effectively discharge static energy and enhance the system's anti-interference capability.

Figure 2 Network Transformer

3、 Design Optimization Suggestions

During actual PCB layout, the following principles should be followed to ensure communication quality:

● Differential Routing: MDI differential pairs must be strictly length-matched and routed in parallel, mainta

● Via Avoidance: Minimize the number of vias on differential lines, and strictly prohibit differential lines  crossing power split zones.

4、 T113 Chip Series and Application Advantages

The Allwinner T113 series processors not only possess outstanding interface expansion capabilities—including series such as T113-i and T113-S3—but also feature differentiated configurations for various industrial scenarios. For example, the T113-S3 integrates 128MB DDR3 RAM internally; this high-integration design greatly optimizes PCB space layout and significantly reduces system costs. Thanks to its strong computing performance and rich peripheral interfaces, the T113 series is widely used in industrial automation control, Human-Machine Interfaces (HMI), Programmable Logic Controllers (PLC), and various IoT smart gateways, making it an ideal choice for industrial-grade embedded applications.

5、 About Weathink

As a deep solution design partner of Allwinner Technology, Weixinke focuses on hardware development and technical support for the T113  With deep experience in circuit design and rigorous EMC testing capabilities, we provide customers with one-stop solutions  schematic review and PCB Layout optimization to driver debugging, helping your products reach the market quickly.